Memory units typically comprise a memory and a memory control unit. A memory control unit typically includes a memory controller that sends various command sequences, such as an initialization command sequence, a write command sequence, a read command sequence, and an auto refresh command sequence to the memory in a predefined pattern. The memory controller can be implemented as a state machine, wherein different states of the state machine specify the command that is to be sent to the memory.
Such state machines for implementing a memory controller are typically implemented, at least to a significant portion, in hardware so that the sequence of commands that is applied to the memory is fixed. Conventionally, after device fabrication, changes in the command sequences are usually difficult or impossible to implement. Since command sequences may vary and since modifications in the command sequences may be difficult or impossible to implement using a conventional state machine implementation of the memory controller, it may be difficult to support different types of memories that employ different command sequences using a conventional state machine implementation. Still further, if different data widths are to be supported, the state machine becomes increasingly complex.
For these and other reasons there is a need for the present invention.